1. Field of the Invention
This invention relates to semiconductor circuits. More particularly, the invention relates to low voltage CMOS circuits for on/off chip high voltage drive.
2. Description of Prior Art
Often times, low voltage CMOS circuits which operate at 3.3 volts must provide higher output voltages which operate at 5.0 volts on or off the same chip. Problems occur when a 3.3 volt chip is connected to higher voltage components. These problems include gate oxide breakdown, hot electron effect, and undesirable reverse leakage. The transistor breakdown can be manifested in at least two forms. The snapback/sustaining voltage occurs when a transistor suddenly transfers from a stable operating point at high drain to source voltage to a lower drain to source voltage at a much higher current. This condition can, under certain conditions, be catastrophic and should be avoided. Another problem is induced stresses causing breakdown condition for MOSFET devices in the gate to drain and the gate to source oxide breakdown voltage. While the snapback/sustaining voltage can be controlled to some extent by using MOSFET's that are two to three times the minimum channel length, there are limits to the use of this technique. The gate to source and gate to drain breakdown voltage limits are not alleviated by this technique. To control these breakdown mechanisms it is necessary to limit all of the aforementioned voltages to the design limits for the particular CMOS technology. For example, it is necessary to limit the drain to source voltage to 3.3 volts or less for technology which is intended for 3.3 volt power supply. Despite the above limitations, it is still desirable to be able to communicate to on or off chip circuits while switching to 5 volt signals without causing breakdown in any of the MOSFET's operating at 3.3 volts.
Prior art related to low voltage CMOS circuits providing higher output voltages include the following:
U.S. Pat. No. 4,709,162 issued Nov. 24, 1987, discloses an off chip driver circuit which includes a pull-up device between an output terminal and a first voltage dropping device diode. A first supply source and a first voltage limiting circuit are connected to the common point between the pull-up device and the voltage dropping diode. The circuit includes means for limiting the voltage at the common point between the voltage dropping diode and the pull-up device to provide high drive to the output terminal without producing excessive stresses in gate oxides and with minimal or no direct current leakage paths.
U.S. Pat. No. 4,429,237 issued Jan. 31, 1984 discloses a pair of FETs connected in series between a potential source and a reference potential. One of the FETs has an input terminal connected to its gate; both of the FETs include a shield surrounding a drain or source diffusion. One of the FETs is connected to the shield of the other and its own shield is connected to a potential source which maybe the potential source connected to the series FETs. This connection aspect provides an FET inverter tolerant of relatively high voltages.
U.S. Pat. No. 4,752,699 issued Jun. 21, 1988 discloses on chip multiple voltage generation using a charge pump and plural feedback sense circuits. A powerdown circuit and a selected feedback path provide a desired voltage level at the output of the charge pump.
U.S. Pat. No. 5,266,849 issued Nov. 30, 1993, discloses a CMOS tri-state buffer circuit which transfers digital signals between a first digital circuit operating at 3.3 volts and a second system operating at 5 volts. Driver clamp circuitry and an n-well voltage controller operate in conjunction with the driver stage to prevent the 5 voltage supply of the second system from interfering with the 3.3 volt system. A clamp line driver transmits signals from the 5 volt system to the 3.3 volt system.
U.S. Pat. No. 5,424,659 issued Jun. 13, 1995, discloses a tri-state buffer circuit for mixed voltage applications. The circuit uses a floating n-well technique in combination with a pass-gate network, a one-shot circuit, and a process-dependent bias voltage reference. The buffer circuit allows CMOS circuits to interface with bus interfaces with higher voltage components, for example, 5 volt peripheral transceiver chips without undesirable reverse leakage currents associated with prior art buffer circuits
U.S. Pat. No. 5,440,249 issued Aug. 8, 1995, discloses a voltage translator circuit in which an input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in an output stage. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translators circuit.
U.S. Pat. No. 5,467,031 issued Nov. 14, 1995, discloses a 3.3 volt CMOS tri-state driver capable of driving a common 5 volt line. A PMOS pull-up transistor and an NMOS pull-down transistor are connected to an output terminal. The pull-up transistors is formed in and has a substrate terminal that is connected to an n-well. A switching transistor is controlled to connect the n-well to the power supply. A pass-gate transistor is biased to turn-off the switching transistor when the voltage at the output terminal is higher than the power supply voltage, the turn-off causing the n-well to float which prevents leakage current from flowing through a semiconductor junction from the output terminals to the n-wells through the pull-up transistor. A shorting transistor is controlled to short the gate of the pull-up transistor to the n-well when the voltage at the output terminal is higher than the power supply voltage, the shorting preventing leakage current from flowing through the channel of the pull-up transistor.
U.S. Pat. No. 5,477,172 issued Dec. 19, 1995, discloses an input buffer which is configurable depending on whether a 5 or 3.3 volt supply voltage is present. The buffer includes two input buffer circuits. Each circuit is connected to a multiplexer in a control circuit. A logic 1 or 0 set in the control circuit selects the proper input of the multiplexer to be outputted as a valid signal depending upon whether the system is operating at 5.0 or 3.3 volts.
U.S. Pat. No. 5,583,454 issued Dec. 10, 1996, discloses a programmable input/output driver circuit including programmable pull-up and pull-down functions. The circuit may be configured into an application having devices powered by a power supply voltage which is substantially larger than the voltage supplying the driver. Additionally, the circuit maybe configured in other applications having devices powered by a power supply voltage substantially similar to the voltage supplying the driver.
None of the above prior art, alone or in combination, discloses or suggests a low voltage CMOS circuit and method of operation which utilizes intermediate voltages and voltage division techniques for multiple CMOS cascode chains between two power rails to provide higher voltages on or off chip whereby the bias voltages for MOS devices in the chains dynamically change to maintain drain to source, gate to drain and gate to source voltages within acceptable limits for device breakdown prevention.